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DATA SHEET
SPHE8281D
DVD Single Chip MPEG A/V Processor
Preliminary
MAY 19, 2005 Version 0.1
Preliminary
SPHE8281D/Dx
Table of Contents
PAGE
1. GENERAL DESCRIPTION............................................................................................................................................................................... 3 2. FEATURE .......................................................................................................................................................................................................... 4 3. BLOCK DIAGRAM ........................................................................................................................................................................................... 6 4. SIGNAL DESCRIPTION ................................................................................................................................................................................... 7 4.1. PIN MAP ..................................................................................................................................................................................................... 7 4.2. GROUP MAP ............................................................................................................................................................................................... 8 4.3. PIN DESCRIPTION........................................................................................................................................................................................ 9 5. FUNCTIONAL DESCRIPTIONS .................................................................................................................................................................... 22 5.1. PLL AND CLOCKGEN ................................................................................................................................................................................ 22 5.2. POWER CONTROL ..................................................................................................................................................................................... 22 5.3. EMBEDDED 32-BIT RISC CONTROLLER..................................................................................................................................................... 22 5.4. ROM/FLASH/SRAM CONTROLLER ........................................................................................................................................................... 23 5.5. CSS DECRYPTION HARDWARE ................................................................................................................................................................. 24 5.6. MPEG VIDEO DECODER........................................................................................................................................................................... 24 5.7. VIDEO POST PROCESSING ........................................................................................................................................................................ 24 5.8. PROGRAMMABLE AUDIO DECODER............................................................................................................................................................ 25 5.9. AUDIO INTERFACE..................................................................................................................................................................................... 25 5.10. AUDIO DAC .............................................................................................................................................................................................. 25 5.11. I/O PROCESSOR ....................................................................................................................................................................................... 25 5.12. SDRAM CONTROLLER ............................................................................................................................................................................. 25 5.13. SUB-PICTURE DECODER ........................................................................................................................................................................... 25 5.14. ON SCREEN DISPLAY ................................................................................................................................................................................ 25 5.15. DISPLAY INTERFACE .................................................................................................................................................................................. 26 5.16. VIDEO DAC .............................................................................................................................................................................................. 26 5.17. GPIO........................................................................................................................................................................................................ 26 5.18. UART ....................................................................................................................................................................................................... 26 6. ELECTRICAL SPECIFICATIONS .................................................................................................................................................................. 27 6.1. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................................. 27 6.2. DC OPERATING CONDITIONS .................................................................................................................................................................... 27 6.3. CAPACITANCE ........................................................................................................................................................................................... 27 6.4. AC CHARACTERISTICS.............................................................................................................................................................................. 28 6.4.1. SDRAM interface timing diagrams .............................................................................................................................................. 28 6.4.2. ROM / flash interface timing diagrams........................................................................................................................................ 29 6.4.3. Audio interface timing diagrams .................................................................................................................................................. 30 6.4.4. Video timing diagrams ................................................................................................................................................................. 31 7. PACKAGE/PAD LOCATION .......................................................................................................................................................................... 33 7.1. OUTLINE DIMENSIONS ............................................................................................................................................................................... 33 8. DISCLAIMER .................................................................................................................................................................................................. 34 9. REVISION HISTORY ...................................................................................................................................................................................... 35
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Preliminary
SPHE8281D/Dx
DVD SINGLE CHIP MPEG A/V PROCESSOR
1.GENERAL DESCRIPTION
SPHE8281D A/V decoder is a single-chip integrated DVD A/V decoder. It is designed to maximize system performance with It integrates DVD/CD controller, host processor, ISO/IEC 11172 MPEG1, 13818 MPEG2 sources. Besides MPEG A/V decoding, it supports Dolby Digital and MPEGI/II Layer1/2, PCM, LPCM audio playback. SPHE8281D also combines all the functions required for a high-performance progressive-scan DVD system. Built-in
minimum cost.
A/V decoding hardware, audio quality DAC and a 6-channel multi-format TV-encoder.
de-interlacing hardware allows high quality DVD playback. The SPHE8281D supports DVD and CD physical formats. For logical formats it supports DVD-Video, Super Video CD, Video CD, CD-DA, OKO, and CD-ROM discs. Development tools of SPHE8281D include complete compiler SPHE8281D performs real-time decoding and playback of tools, programming guide and system application libraries. embedded digital audio decoder is able to support key control and audio sound effects for Karaoke.
Application utilizing the SPHE8281D is presented below:
IR
VFD front panel
4-ch video output
SPHE8281D
2-ch audio analog output 2~8ch
DVD-loader
Audio DAC
Audio amplifier
SDRAM ROM
USB devices
Figure 1-1 Sample SPHE8281D application
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2.FEATURE
Single Chip Integrated DVD Servo and A/V Decoder Integrated DVD/CD Servo Controller -- Support 1x ~ 2x DVD format reading -- Support 1x ~ 8x CD format reading Embedded 32-bit RISC Processor without external host controller Embedded Audio Processor supports multiple audio standards Embedded 8-bit I/O processor supports programmable SDRAM controller -- High Performance SDRAM controller -- Support 16 or 32 bit operation -- Support up to 2 SDRAM devices -- Support 16M/64M SDRAM devices Video Display -- De-interlacing of interlaced video source -- Flexible vertical interpolation -- Flexible horizontal interpolation with optional CIF filter -- Powerful cropping and panning effect -- Support YUV422, 8-bit indexed color format OSD -- Multiple OSD regions with different formats -- Support 2/4/16 indexed color -- Support 16/24-bit direct color Embedded TV encoder -- Simultaneous multi-channel output -- Support 480i/480p/576i/576p format -- Support CVBS and S-Video output -- Support Component (YUV / YPbPr) or SCART-RGB output -- Support WSS and CGMS/A -- Macrovision Interface -- 27MHz crystal driver -- 16/32-bit SDRAM interface -- 8-bit ROM/FLASH/SRAM interface -- One UART port -- IR and VFD support -- 4-channel 12-bit video DAC analog output -- Simultaneous 8-channel audio DAC output -- IEC958/SPDIF digital input / output -- 2-channel 24-bit audio DAC analog output -- External ADC digital input interface (optional) -- Optional ATAPI and I2S interface support -- Optional Parallel Port interface support Low power
TM 1 TM 3
interface control Embedded TV encoder with multi-channel built-in high-speed video DAC supports various display standards Embedded 2-channel 24-bit audio DAC Built-in system PLL and audio PLL generate all clock sources required from single 27MHz crystal input Support following disc format: -- DVD Navigation 1.0 -- SVCD (Chaoji VCD) -- OKO disc -- VCD 2.0/1.1/1.0 -- CDDA / HDCD -- CDROM (game, WMA and JPEG disc) CSS/CPPM hardware -- Built-in CSS hardware -- Built-in CPPM C2_DCBC and C2_D/C2_E function Video Decoder -- Real time MPEG2 MP@ML decoding -- Real time MPEG4 ASP D1 resolution decoding -- Real time MPEG1 D1 (720x480x30 /720x576x25) decoding -- DivX 3.11, 4.0 and 5.x version compatible -- Hardware accelerated JPEG decoding -- Advanced decoding and display control Sub-picture Decoder -- Advanced Sub-Picture Decoder for DVD SVCD and OKO -- Support hardware vertical scaling Audio Decoder -- Flexible Programmable DSP Architecture -- Support CDDA -- Support LPCM, PCM, and WMA playback -- Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with optional down-mixing) -- Support Dolby
TM 2
7.1.D1 and Macrovision AGC v1.03
analog copy protection
-- Advanced low power design -- Selective standby mode -- Programmable low speed operation Technology -- Advanced CMOS technology -- 216-pin LQFP package -- 3v (I/O) and 1.8v (kernel) power supplies -- 5v I/O tolerance
Digital AC3 playback
-- Support Key Shift of 2 channels -- Support equalization, reverb and special sound field
1 2
WMA is a trademark of Microsoft Corporation Dolby is a trademark of the Dolby Laboratories 4
3
Macrovision is a trademark of Macrovision Corporation MAY. 19, 2005 Preliminary Version: 0.1
(c) Sunplus Confidential Contents are subject to change without Notice
Preliminary
SPHE8281D/Dx
%
Licensing Notice In order to take care of different royalties, Sunplus SPHE8281D series have different combinations for different royalties. For detail information, please contact with Sunplus Sales. Supply of the implementation of Dolby, WMA, Macrovision ... technologies do not imply of a right or convey a license under any patent, or any Intellectual Property Right of each respective company. Companies plan to use the implementations MUST obtain respective license from respective licensor. Additional royalties may be required and are to be paid by purchaser to each respective licensor Dolby is a trademark of the Dolby Laboratories. "This product includes technology owned by Dolby Laboratories cannot be used or further distributed without a license from Dolby Laboratories." WMA is a trademark of Microsoft Corporation. "This product includes technology owned by Microsoft Corporation cannot be used or further distributed without a license from Microsoft." DivX is a trademark of the DivXNetworks Inc. "This product includes technology owned by DivXNetworks Inc. cannot be used or further distributed without a license from DivXNetworks Inc." Macrovision is a trademark of the Macrovision Corporation. "This product includes technology owned by Macrovision Corporation cannot be used or further distributed without a license from Macrovision Corporation." All other trademarks are owned and trademarks of their respective holders and companies, which are used for identification purposed only
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SPHE8281D/Dx
3.BLOCK DIAGRAM
EPROM/SRAM
EPROM/ SRAM interface
RISC
icache dcache
PLLv PLLa
Power control
Servo Control RF
loader inf.
loader RF input
USB1.1 bus
USB 1.1 host
Intr. control Timer RISC DMA
Audio DSP
icache mem
ECC
SDRAM /16 or /32
SDRAM controller
Bootstrap HOST DMA
I/O processor GPIO UART DAC
IR/VFD/(I2C) GPIO UART
Video encoder
Video output
OSD decoder Sub-picture decoder Video postprocessing
DAC analog out
Video DAC
MPEG video decoder
Audio Interface
IEC 958 I/O ADC digital in
Figure 3-1 SPHE8281D block diagram
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4.SIGNAL DESCRIPTION
4.1. Pin Map
162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
R_A12 R_A7 R_A6 R_A5 R_A4 R_A3 R_A2 R_A1 R_A0 R_D0 R_D1 R_D2 VSS_O5/VSS_K5 R_D3 R_D4 R_D5 R_D6 R_D7 R_OE_B VDD_K4 M_DQM2/GPIO M_DQM3/GPIO R_A10 R_A11 R_A9 R_A8 VDD_O4 R_A13 R_A14 R_A17 R_WE_B M_A3 M_A2 M_A1 VSS_O4/VSS_K4 M_A0 M_A10 M_BA1/GPIO M_DQM0/GPIO M_DQM1/GPIO M_A4 VDD_K3 M_A5 M_A6 M_A7 M_A8 M_A9 M_CKE/GPIO VSS_O3/VSS_K3 M_CLKO VDD_O3 M_A11/GPIO M_D8 M_D9
R_A15 DAC_REF DAC_L DAC_R DAC_VDD DAC_VSS R_A16 R_A18 A_IEC_TX/GPIO A_DATA0/GPIO VDD_O5 A_DATA1/GPIO A_DATA2/GPIO A_DATA3/GPIO A_LRCK/GPIO VSS_K6/VSS_O6 A_BCK/GPIO A_XCK/GPIO UA0_RX/GPIO UA0_TX/GPIO V_COMP V_BIAS V_FSADJ V_REFOUT TV_DAC0 VDD_TVA0 VSS_TVA0 VDD_TVA1 VSS_TVA1 TV_DAC3 TV_DAC4 VDD_TVA2 TV_DAC5 VSS_TVA2 PLL_AVDD LPFO LPFN VREFO PDFLT FDFLT LPFNIN LGIN PLL_DS_AVSS RFI CNIN SLVL DS_AVDD RF_AVDD GMRES AGCCAP RFRP RFO FLTIP FLTIN
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
SPHE8281D
8202D-216P 216 PIN LQFP 24x24mm2
M_D10 M_D11 M_D12 VDD_K2 M_D13 M_D14 M_D15 M_BA0 M_CS0_B/GPIO VSS_O2/VSS_K2 M_RAS_B M_CAS_B M_WE_B M_D0 M_D1 M_D2 VDD_O2 M_D3 M_D4 M_D5 M_D6 M_D7 VDD_PLLV VSS_PLLV VDD_PLLA VSS_PLLA USB_DM USB_DP USB_VDD USB_GND CLKOUT CLKIN R_A19 R_A20/E_MX10 VFD_DATA/GPIO VFD_STB/GPIO VFD_CLK/GPIO IR_IN/GPIO RST_B R_CS1_B/GPIO R_CS2_B/GPIO R_CS3_B/GPIO R_CS4_B/GPIO GPIO VDD_O1 GPIO/ttio3_7 GPIO/ttio2_6 GPIO/ttio1_5 VSS_O1/VSS_K1 GPIO/ttio0_4 GPIO/TRAY_IS_OUT GPIO/TRAY_IS_IN VDD_K1 DFCT/GPIO
AGCON AGCOP RFIP RFIS RFSUM DPDA DPDB DPDC DPDD DVDD DVDC DVDB DVDA CDB CDA CDF CDE RF_AVSS APC_AVSS DVDLDO CDLDO DVDMDI CDMDI APC_SRV_AVDD V21 R33K V165 SVOTST RFRPPH RFRPBH RFRPMEAN SBADPH SBAD FEO TEO TEOLP OPVIP OPVIN OPVOP SRV_AD_AVSS_VRGD AD_DA_AVDD DATEO DAFEO DA_AVSS E_MX8 E_MX9 SPDC_OUT/GPIO SC_OUT/GPIO SC1_OUT/GPIO TRAY_OUT/GPIO DMEA/GPIO FGIN/GPIO HOMESW/GPIO LDSW/GPIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Figure 4-1 SPHE8281D pin
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4.2. Group Map
VSS_*
LPFO LPFN VREFO PDFLT FDFLT LPFNIN LGIN RFI CNIN SLVL GMRES AGCCAP RFRP RFO FLTIP FLTIN AGCON AGCOP RFIP RFIS RFSUM
System Interface Audio analog output interface Audio digital output interface
VDD_* CLKIN / CLKOUT RSTB DAC_VREF DAC_L DAC_R AU_XCK AU_BCK AU_LRCK AU_DATA[3:0] A_IEC_TX
R_CS_B[3:0]
DPDA DPDB DPDC DPDD DVDA DVDB DVDC DVDD CDB CDA CDF CDE DVDLDO CDLDO DVDMDI CDMDI
ROM/flash interface
R_OE_B R_WE_B R_A[19:0] R_D[7:0] M_CLKO M_RAS_B M_CAS_B M_WE_B M_CS0_B M_BA0 M_BA1 M_A11 M_A[10:0] M_D[15:0] M_DQM[3:0] IR_IN
SERVO
SPHE8281D (216pin)
R33K V165 SVOTST SBADPH SBAD FEO TEO TEOLP OPVIP OPVIN OPVOP VRGD DATEO DAFEO SPDC_OUT SC_OUT SC1_OUT TRAY_OUT DMEA FGIN HOMESW LDSW DFCT TRAY_IS_OUT TRAY_IS_IN ttio*
SDRAM interface
RFRPPH RFRPBH RFRPMEAN
IR VFD UART GPIOs
VFD_CLK VFD_STB VFD_DATA UA0_RX UA0_TX Other GPIOs V_COMP V_BIAS V_FSADJ V_REFOUT V_DAC0 V_DAC3 V_DAC4 V_DAC5
SERVO
Video output interface
Figure 4-2 SPHE8281D pin groups
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4.3. Pin Description
Symbol AGCON AGCOP RFIP RFIS RFSUM DPDA DPDB DPDC DPDD DVDD DVDC DVDB DVDA CDB CDA CDF CDE RF_AVSS APC_AVSS DVDLDO CDLDO DVDMDI CDMDI APC_SRV_AVDD V21 R33K V165 SVOTST RFRPPH RFRPBH RFRPMEAN SBADPH SBAD FEO TEO TEOLP OPVIP OPVIN OPVOP SRV_AD_VRGD_AV SS AD_DA_AVDD DATEO DAFEO (c) Sunplus Confidential Contents are subject to change without Notice 41 42 43 S A A 9 MAY. 19, 2005 Preliminary Version: 0.1 Servo ADC/DAC 3.3V power Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O O O I I O I I I I I I I I I I I I S S O O I I S O O O O O O O O A I I O S Op-amp 1 positive input. Op-amp 1 negative input. Op-amp output. Servo/ADC analog ground Differential AGC output #N Differential AGC output #P Differential RF signal input #P Single-ended RF equalizer input. RF summing amplified output. AC coupled RF inputs for the DPD #A, from the main beam photo detector. AC coupled RF inputs for the DPD #B, from the main beam photo detector. AC coupled RF inputs for the DPD #C, from the main beam photo detector. AC coupled RF inputs for the DPD #D, from the main beam photo detector. DVD RF inputs #A, from the main beam photo detector. DVD RF inputs #B, from the main beam photo detector. DVD RF inputs #C, from the main beam photo detector. DVD RF inputs #D, from the main beam photo detector. CD RF inputs #B, from the main beam photo detector. CD RF inputs #A, from the main beam photo detector. CD tracking error inputs #F, from the sub-beam photo detector. CD tracking error inputs #E, from the sub-beam photo detector. Servo RF ground Servo APC ground DVD APC output. CD APC output. DVD APC input from monitor photo diode. CD APC input from monitor photo diode. Servo APC and analog 3.3V power (216pin only) Reference DC bias voltage. External reference resistor input. Reference DC bias voltage. RF peak hold external capacitor RFRP peak hold signal output. RFRP bottom hold signal output. RFRP mean signal output. Sub-beam adds peak hold signal output. Sub-beam adds signal output. Focus error signal output. Tracking error signal output. Description
Preliminary
SPHE8281D/Dx
Symbol DA_AVSS E_MX8 Pin No. 44 45 I/O S I/O Servo DAC ground GPIO [70] Priority selection sft_cfg2[5:4] =2'b01 sft_cfg7[5:4]=2'b11 sft_cfg1[11:9]=3'b110 sft_cfg7[1]= 1'b 0, sft_cfg0[11]= 1'b 1, fm_gpio_len[3:0]>8 sft_cfg0[11]= 1'b 0, fm_gpio_len[3:0]=4'b1100 Sft_cfg8[5]= 1'b 1 (other) E_MX9 46 I/O GPIO[71] Priority selection sft_cfg2[5:4] =2'b01 sft_cfg7[5:4]=2'b11 sft_cfg1[11:9]=3'b110 sft_cfg7[1]= 1'b 0, sft_cfg0[11]= 1'b 1, fm_gpio_len[3:0]>8 sft_cfg0[11]= 1'b 0, fm_gpio_len[3:0]=4'b1100 Sft_cfg8[5]= 1'b 1 (other) SPDC_OUT/GPIO 47 I/O Servo SPDC_OUT Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[0]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) SC_OUT/GPIO 48 I/O Servo SC_OUT Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[1]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) SC1_OUT/GPIO 49 I/O Servo SC1_OUT Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[2]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) (c) Sunplus Confidential Contents are subject to change without Notice 10 Function AT_DIOW_B SC1_OUT (default) DAC_PDD OTP_TEST_ADDR[2] GPIO[2] dir O I/O I I I/O MAY. 19, 2005 Preliminary Version: 0.1 Function AT_DIOR_B SC_OUT (default) DAC_PDE OTP_TEST_ADDR[1] GPIO[1] dir O I/O I I I/O Function AT_RESET_B SPDC_OUT (default) DAC_PDF OTP_TEST_ADDR[0] GPIO[0] dir O I/O I I I/O TV_EXT_DATA_Cr[6] GPIO[71](default) I I/O FM_GPIOB [30] I/O Function UA1_TXD 656_DATA[1] RISC_INT1_12 FM_GPIOB [13] dir O O I I/O TV_EXT_DATA_Cr[7] GPIO[70](default) I I/O FM_GPIOB [29] I/O Function UA1_RXD 656_DATA[0] RISC_INT1_11 FM_GPIOB [12] Dir I O I I/O Description
Preliminary
SPHE8281D/Dx
Symbol TRAY_OUT/GPIO Pin No. 50 I/O I/O Servo TRAY_OUT Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[3]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) DMEA_OUT/GPIO 51 I/O Servo DMEA Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[4]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) FGIN/GPIO 52 I/O Servo FGIN Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[5]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg8[8]=1'b1 (other) HOMESW/GPIO 53 IO Servo HOMESW Priority selection sft_cfg2[3:2]=2'b10 sft_cfg1[8:6]=3'b010 sft_cfg7[7:6]=2'b11 Sft_cfg8[1]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg9[14:13]=2'b01 sft_cfg6[4]=1'b1 sft_cfg8[8]=1'b1 (other) LDSW/GPIO 54 IO Servo LDSW Priority selection sft_cfg2[3:2]=2'b10 sft_cfg2[5:4]=2'b10 sft_cfg7[7:6]=2'b11 Sft_cfg8[2]=1'b1 Sft_cfg8[9]=1'b1 sft_cfg7[15:14]=2'b11 sft_cfg9[14:13]=2'b10 sft_cfg6[4]=1'b1 (other) Function UA0_TXD UA1_RXD PCMCIA_IOR_B DSP_FL1 DAC_DATA_F[8] CLK27_OUT EXT_CLK48 DELAY_CHAIN2 GPIO[7] (default) dir O I O O I O I O I/O Function UA0_RXD R_CSALL_B PCMCIA_IOW_B DSP_FL0 DAC_DATA_F[9] EXT_CLK48 DELAY_CHAIN1 OTP_TEST_DATA GPIO[6] (default) dir I O O O I I O O I/O Function AT_DMARQ FGIN (default) DAC_PDA OTP_TEST_PGM GPIO[5] dir I I I I I/O Function AT_DMACK DMEA_OUT (default) DAC_PDB OTP_TEST_ADDR[4] GPIO[4] dir O O I I I/O Function AT_IORDY TRAY_OUT (default) DAC_PDC OTP_TEST_ADDR[3] GPIO[3] dir I I/O I I I/O Description
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Symbol DFCT/GPIO Pin No. 55 I/O IO Servo DFCT Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[6]=1'b1 Sft_cfg8[9]=1'b1 (other) VDD_K1 GPIO/TRAY_IS_IN 56 57 S IO Kernel logic power supply #1 GPIO Priority selection sft_cfg2[11:10]=2'b01,2'b10 Sft_cfg8[3]=1'b1 fm_gpio_len[3:0] > 0 Sft_cfg8[9]=1'b1 (other) GPIO/TRAY_IS_OUT 58 IO GPIO Priority selection sft_cfg2[11:10]=2'b01,2'b10 Sft_cfg8[4]=1'b1 fm_gpio_len[3:0] > 0 Sft_cfg8[9]=1'b1 (other) GPIO/ttio0_4 59 IO GPIO Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[9]=1'b1 Sft_cfg1[11:9]=3'b001 Sft_cfg3[11:10]=2'b01 Function AT_ADR[0] ttio4/ttio0 RISC_INT1_11 ADC_BCK, digital audio input interface bit clock fm_gpio_len[3:0] > 0 Sft_cfg8[9]=1'b1 (other) VSS_O1/ VSS_K1 GPIO/ttio1_5 60 61 S IO FM_GPIOB[2] DAC_DATA_F[4] GPIO[11] (default) I/O I I/O dir O I/O I I/O Function AT_ADR[2] DSP_FLAG_OUT FM_GPIOB[1] DAC_DATA_F[5] GPIO[10] (default) dir O O I/O I I/O Function AT_ADR[1] DSP_FL2 FM_GPIOB[0] DAC_DATA_F[6] GPIO[9] (default) dir O O I/O I I/O Function AT_INTRQ DFCT (default) DAC_DATA_F[7] GPIO[8] dir I O I I/O Description
Kernel logic / I/O power shared ground supply #1 GPIO Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[9]=1'b1 sft_cfg4[15:13]=3'b001 Sft_cfg1[11:9]=3'b001 Sft_cfg3[11:10]=2'b01 Function AT_CS1 Ttio5/ttio1 HSYNC_PC RISC_INT1_12 ADC_LRCK, digital audio input interface L/R strobe fm_gpio_len[3:0] > 0 Sft_cfg8[9]=1'b1 (other) FM_GPIOB[3] DAC_DATA_F[3] GPIO[12] (default) I/O I I/O dir O I/O O I I/O
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Preliminary
SPHE8281D/Dx
Symbol GPIO/ttio2_6 Pin No. 62 I/O IO GPIO Priority selection sft_cfg2[11:10]=2'b01,2'b10 sft_cfg4[9]=1'b1 sft_cfg4[15:13]=3'b001 sft_cfg3[15:14]=2'b01 Sft_cfg1[11:9]=3'b001 Sft_cfg3[11:10]=2'b01 Function AT_CS0 Ttio6/ttio2 VSYNC_PC ISA_IOCHRDY RISC_INT1_13 ADC_DATA, digital audio input interface data fm_gpio_len[3:0] > 1 Sft_cfg8[9]=1'b1 (other) GPIO/ttio3_7 63 IO GPIO Priority selection sft_cfg4[9]=1'b1 sft_cfg2[9:8]=2'b11 sft_cfg7[11:8]=4'b0001 Sft_cfg1[11:9]=3'b001 fm_gpio_len[3:0] > 2 Sft_cfg8[9]=1'b1 (other) VDD_O1 GPIO 64 65 S IO I/O power supply #1 GPIO Priority selection sft_cfg2[5:4]=2'b10 sft_cfg1[8:6]=3'b001 sysclk_sel[4] sft_cfg7[11:8]=4'b0010 fm_gpio_len[3:0] > 3 sft_cfg8[9]=1'b1 sft_cfg7[13:12]=2'b11 sft_cfg9[14:13]=2'b11 sft_cfg6[4]=1'b1 (other) R_CS4_B/GPIO 66 IO Function UA1_TXD R_CSALL_B EXT_SYSCLK EXT_CLK27 FM_GPIOB[6] DAC_DATA_F[0] CLK54_OUT EXT_CLK48 DELAY_CHAIN3 GPIO[15] (default) dir O O I I I/O I O I O I/O Function Ttio7/ttio3 PCMCIA_WAIT_B EXT_CLK27 RISC_INT1_14 FM_GPIOB[5] DAC_DATA_F[1] GPIO[14] (default) dir I/O I I I I/O I I/O FM_GPIOB[4] DAC_DATA_F[2] GPIO[13] (default) I/O I I/O dir O I/O O I I I Description
ROM / SRAM / flash chip select #4 or GPIO Priority selection sft_cfg1[3]=1'b1 sft_cfg1[7]=1'b1 & fm_gpio_len[3:0] = 10,11,12 sft_cfg8[9]=1'b1 (other) DAC_DATA_E[9] GPIO[16] I I/O Function R_CS4_B (default) FM_GPIOB[20] dir O I/O
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Preliminary
SPHE8281D/Dx
Symbol R_CS3_B/GPIO Pin No. 67 I/O IO Description ROM / SRAM / flash chip select #3 or GPIO Priority selection sft_cfg1[2]=1'b1 sft_cfg8[9]=1'b1 (other) R_CS2_B/GPIO 68 IO Function R_CS3_B (default) DAC_DATA_E[8] GPIO[17] dir O I I/O
ROM / SRAM / flash chip select #2 or GPIO Priority selection sft_cfg1[1]=1'b1 sft_cfg8[9]=1'b1 (other) Function R_CS2_B (default) DAC_DATA_E[7] GPIO[18] dir O I I/O
R_CS1_B/GPIO
69
IO
ROM / SRAM / flash chip select #1 or GPIO Priority selection sft_cfg1[0]=1'b1 sft_cfg8[9]=1'b1 (other) Function R_CS1_B (default) DAC_DATA_E[6] GPIO[19] dir O I I/O
RST_B IR_IN/GPIO
70 71
I IO
System reset (active low reset) GPIO Priority selection sft_cfg8[0]=1'b1 (other) Function IR_IN,GPIO[20] GPIO[20] (default) dir I I/O
VFD_CLK/GPIO VFD_STB/GPIO
72 73
IO IO
GPIO[21] for VFD_CLK GPIO[22] for VFD_STB Priority selection sft_cfg8[9]=1'b1 (other) Function DAC_DATA_E[5] GPIO[22] (default) dir I I/O
VFD_DATA/GPIO
74
IO
GPIO[23] for VFD_DATA Priority selection sft_cfg8[9]=1'b1 (other) Function DAC_DATA_E[4] GPIO[23] (default) dir I I/O
R_A20 R_A19 (E_MX11) CLKIN CLKOUT RESERVED_N RESERVED_P RESERVED RESERVED VSS_PLLA VDD_PLLA VSS_PLLV VDD_PLLV M_DD[7] M_DD[6] M_DD[5] M_DD[4] (c) Sunplus Confidential
75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
IO IO I O A A A A S S S S IO IO IO IO
ROM / SRAM / flash address bus bit [20] (216pin package) ROM / SRAM / flash address bus bit [19] Clock input / crystal in (XTALI) Clock output / crystal out (XTALO) Reserved Reserved Reserved Reserved Ground pin for audio PLL 3.3V power supply pin for audio PLL Ground pin for system PLL and audio PLL 1.8V power supply pin for system PLL SDRAM data bus [7] SDRAM data bus [6] SDRAM data bus [5] SDRAM data bus [4] 14 MAY. 19, 2005 Preliminary Version: 0.1
Contents are subject to change without Notice
Preliminary
SPHE8281D/Dx
Symbol M_DD[3] VDD_O2 M_DD[2] M_DD[1] M_DD[0] M_WE_B M_CAS_B M_RAS_B VSS_O2/ VSS_K2 M_CS0_B/GPIO Pin No. 91 92 93 94 95 96 97 98 99 100 I/O IO S IO IO IO IO IO IO S IO SDRAM data bus [3] I/O power supply #2 SDRAM data bus [2] SDRAM data bus [1] SDRAM data bus [0] SDRAM write enable / row precharge SDRAM column address strobe (CASB) SDRAM row address strobe (RASB) Kernel logic / I/O power shared ground supply #2 SDRAM chip select 0, or GPIO[24] Priority selection sft_cfg0[0]=1'b1 Function SDRAM chip select (default) sft_cfg8[9]=1'b1 (other) M_BA0 M_DD[15] M_DD[14] M_DD[13] VDD_K2 M_DD[12] M_DD[11] M_DD[10] M_DD[9] M_DD[8] M_A[11]/ GPIO 101 102 103 104 105 106 107 108 109 110 111 IO IO IO IO S IO IO IO IO IO IO SDRAM bank select address [0] SDRAM data bus [15] SDRAM data bus [14] SDRAM data bus [13] Kernel logic power supply #2 SDRAM data bus [12] SDRAM data bus [11] SDRAM data bus [10] SDRAM data bus [9] SDRAM data bus [8] SDRAM address bus [11] or GPIO[25] Priority selection sft_cfg1[4]=1'b1 Function SDRAM address bus M_A[11] (default) sft_cfg8[9]=1'b1 (other) VDD_O3 M_CLKO VSS_O3/ VSS_K3 M_CKE/GPIO 112 113 114 115 S O S IO I/O power supply #3 SDRAM clock output Kernel logic / I/O power shared ground supply #3 SDRAM clock enable, or GPIO[26] Priority selection sft_cfg0[1]=1'b1 Function DRAM clock enable (default) sft_cfg8[9]=1'b1 (other) M_A[9] M_A[8] M_A[7] M_A[6] M_A[5] (c) Sunplus Confidential Contents are subject to change without Notice 116 117 118 119 120 IO IO IO I/O I/O SDRAM address bus [9] SDRAM address bus [8] SDRAM address bus [7] SDRAM address bus [6] SDRAM address bus [5] 15 MAY. 19, 2005 Preliminary Version: 0.1 DAC_DATA_C[1] GPIO[26] I I/O dir O DAC_DATA_C[2] GPIO[25] I I/O dir O DAC_DATA_D[2] GPIO[24] I I/O dir O Description
Preliminary
SPHE8281D/Dx
Symbol VDD_K3 M_A[4] M_DQM1/GPIO M_DQM0/GPIO Pin No. 121 122 123 124 I/O S I/O I/O I/O Kernel logic power supply #3 SDRAM address bus [4] SDRAM data input/output mask for M_DD[15:8], or GPIOA[27] SDRAM data input/output mask for M_DD[7:0] or GPIOA[28] Priority selection sft_cfg0[2]=1'b1 Function SDRAM data input/output mask for M_DD[7:0] (default) sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) M_BA1/GPIO 125 I/O ADC_MONO_D_R[5] DAC_DATA_B[3] GPIO[28] O I I/O dir I/O Description
SDRAM bank select address [1] or GPIOA[29] Priority selection sft_cfg0[6]=1'b1 Function SDRAM bank select address [1] (default) sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) ADC_MONO_D_R[6] DAC_DATA_B[2] GPIO[29] O I I/O dir I/O
M_A[10] M_A[0] VSS_O4/ VSS_K4 M_A[1] M_A[2] M_A[3] R_WE_B R_A17 R_A14 R_A13 VDD_O4 R_A8 R_A9 R_A11 R_A10
126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
O O S O O O I/O I/O I/O I/O S O O I/O O
SDRAM address bus [10] SDRAM address bus [0] Kernel logic / I/O power shared ground supply #4 SDRAM address bus [1] SDRAM address bus [2] SDRAM address bus [3] ROM / SRAM / flash write strobe ROM / SRAM / flash address bus bit [17] ROM / SRAM / flash address bus bit [14] ROM / SRAM / flash address bus bit [13] I/O power supply #4 ROM / SRAM / flash address bus bit [8] ROM / SRAM / flash address bus bit [9] ROM / SRAM / flash address bus bit [11] ROM / SRAM / flash address bus bit [10]
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SPHE8281D/Dx
Symbol M_DQM3/GPIO Pin No. 141 I/O I/O Description SDRAM data input/output mask for M_DD[31:24] , or GPIO[38] Priority selection sft_cfg0[5]=1'b1 Function SDRAM data input/output mask for M_DD[31:24] (default) sft_cfg2[3:2]=2'b11 sft_cfg1[8:6]=3'b011 sft_cfg3[13:12]=2'b10 sft_cfg4[15:13]=3'b010 sft_cfg7[7:6]=2'b01 sft_cfg0[13:12]=2'b01 sft_cfg7[1]= 1'b0, sft_cfg0[11]= 1'b 0, fm_gpio_len[3:0]>9 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 sft_cfg8[10]=1'b1 (other) M_DQM2/GPIO 142 I/O ADC_MONO_D_L[5] DAC_OPA[1] OGT_BIST_FAIL GPIO[38] O I O I/O UA0_RXD R_CSALL_B TV_HSYNC TV_HSYNC_PC PCMCIA_IOW_B TV_LCD_G[2] FM_GPIOB[19] I O I/O O O O I/O dir O
SDRAM data input/output mask for M_DD[23:16] , or GPIO[39] Priority selection sft_cfg0[4]=1'b1 Function SDRAM data input/output mask for M_DD[23:16] (default) sft_cfg2[3:2]=2'b11 sft_cfg3[13:12]=2'b10 sft_cfg4[15:13]=3'b010 sft_cfg7[7:6]=2'b01 sft_cfg0[13:12]=2'b01 sft_cfg7[1]= 1'b 0, sft_cfg0[11]= 1'b 0, fm_gpio_len[3:0]>9 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 sft_cfg8[10]=1'b1 ADC_MONO_D_L[6] DAC_OPA[2] BUF_CTRL_BIST_FAI L (other) GPIO[39] I/O O I O UA0_TXD TV_VSYNC TV_VSYNC_PC PCMCIA_IOR_B TV_LCD_G[3] FM_GPIOB[18] O I/O O O O I/O dir O
VDD_K4 R_OE_B R_D7 R_D6 R_D5 R_D4 R_D3 VSS_O5/ VSS_K5 (c) Sunplus Confidential
143 144 145 146 147 148 149 150
S I/O I/O I/O I/O I/O I/O S
Kernel logic power supply #4 ROM / SRAM / flash output enable ROM / SRAM / flash data bus bit [7] ROM / SRAM / flash data bus bit [6] ROM / SRAM / flash data bus bit [5] ROM / SRAM / flash data bus bit [4] ROM / SRAM / flash data bus bit [3] Kernel logic / I/O power shared ground supply #5 17 MAY. 19, 2005 Preliminary Version: 0.1
Contents are subject to change without Notice
Preliminary
SPHE8281D/Dx
Symbol R_D2 R_D1 R_D0 R_A0 R_A1 R_A2 R_A3 R_A4 R_A5 R_A6 R_A7 R_A12 R_A15 DAC_VREF DAC_L DAC_R DAC_VDD DAC_VSS R_A16 R_A18 A_IEC_TX/GPIO Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 I/O I/O I/O I/O O O O O O O O O I/O I/O A A A S S I/O I/O I/O ROM / SRAM / flash data bus bit [2] ROM / SRAM / flash data bus bit [1] ROM / SRAM / flash data bus bit [0] ROM / SRAM / flash address bus bit [0] ROM / SRAM / flash address bus bit [1] ROM / SRAM / flash address bus bit [2] ROM / SRAM / flash address bus bit [3] ROM / SRAM / flash address bus bit [4] ROM / SRAM / flash address bus bit [5] ROM / SRAM / flash address bus bit [6] ROM / SRAM / flash address bus bit [7] ROM / SRAM / flash address bus bit [12] ROM / SRAM / flash address bus bit [15] Audio DAC reference voltage, connect a 0.1uF to ground Audio DAC left-channel output Audio DAC right-channel output 3.3v power supply for on-chip audio DAC Ground pin for on-chip audio DAC ROM / SRAM / flash address bus bit [16] ROM / SRAM / flash address bus bit [18] IEC-958 transmit data Priority selection sft_cfg3[8]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) A_DATA[0] / GPIO 172 I/O Function A_IEC_TX (default) ADC_MONO_C[0] DAC_OPF[0] GPIO[52] Dir O I I I/O Description
Serial audio data output for channel 1/0 or GPIO Priority selection sft_cfg3[1]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_DATA[0] (default) ADC_MONO_C[1] DAC_OPF[1] GPIO[53] Dir O I I I/O
VDD_O5 A_DATA[1] / GPIO
173 174
S I/O
I/O power supply #5 Serial audio data output for channel 3/2 or GPIO Priority selection sft_cfg3[2]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_DATA[1] (default) ADC_MONO_C[2] DAC_OPF[2] GPIO[54] Dir O I I I/O
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SPHE8281D/Dx
Symbol A_DATA[2] / GPIO Pin No. 175 I/O I/O Description Serial audio data output for channel 5/4 or GPIO Priority selection sft_cfg3[3]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_DATA[2] (default) ADC_MONO_PWAD DAC_PDALL GPIO[55] Dir O I I I/O
A_DATA[3] / GPIO
176
I/O
Serial audio data output for channel 7/6 or GPIO Priority selection sft_cfg3[4]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_DATA[3] (default) ADC_MONO_SPGA DAC_TEST GPIO[56] Dir O I I I/O
A_LRCK/GPIO
177
I/O
PCM data output L/R strobe Priority selection sft_cfg3[6]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_LRCK (default) ADC_MONO_MODE1 DAC_UD GPIO[57] dir I/O I I I/O
VSS_O6/ VSS_K6 A_BCK/GPIO
178 179
S I/O
Kernel logic / I/O power shared ground supply #6 PCM bit clock Priority selection sft_cfg3[0]=1'b1 sft_cfg8[8]=1'b1 Function A_BCK (default) ADC_MONO_MODE1 _1 sft_cfg8[9]=1'b1 (other) DAC_BGPD GPIO[58] I I/O Dir I/O I
A_XCK/GPIO
180
I/O
Audio over-sampling clock Priority selection sft_cfg3[9]=1'b1 sft_cfg8[8]=1'b1 sft_cfg8[9]=1'b1 (other) Function A_XCK (default) ADC_MONO_MODE2 DAC_CLK GPIO[59] Dir I/O I I I/O
UA0_RX/GPIO
181
I/O
UART #0 data receive or GPIO Priority selection sft_cfg2[3:2] =2'b01 sft_cfg3[13:12]=2'b01 sft_cfg4[15:13]=3'b011 (other) Function UART0_RX (default) TV_HSYNC HSYNC_PC GPIO[60] Dir I I/O O I/O
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Preliminary
SPHE8281D/Dx
Symbol UA0_TX/GPIO Pin No. 182 I/O I/O UART #0 data transmit or GPIO Priority selection sft_cfg2[3:2] =2'b01 sft_cfg3[13:12]=2'b01 sft_cfg4[15:13]=3'b011 (other) Function UART0_TX (default) TV_VSYNC VSYNC_PC GPIO[61] Dir O I/O O I/O Description
V_COMP
183
A
(VDAC CBU) Compensation pin. Connect a 0.1pF ceramic capacitor to bypass this pin to VSSA. The lead length must be kept as short as possible to avoid noise.
V_BIAS
184
(VDAC CBL) Bias voltage. Connect a 0.1pF ceramic capacitor to bypass this pin to VSSA. The lead length must be kept as short as possible to avoid noise.
V_FSADJ
185
A
Full-Scale adjustment control pin. The full-scale current of D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground.
V_REFOUT
186
A
(VDAC VREF/bandgap output) Voltage reference output. It generates typical 1.2V voltage reference and may be used to drive V_REFIN pin directly.
V_DAC[0]
187
A
Video DAC output #0. This is a high-impedance current source output. These outputs can drive a 37.5 load directly.
VDD_TVA0 VSS_TVA0 VDD_TVA1 VSS_TVA1 V_DAC[3]
188 189 190 191 192
S S S S A
TV DAC power supply #0 TV DAC ground pin #0 TV DAC power supply #1 TV DAC ground pin #1 Video DAC output #3. This is a high-impedance current source output. These outputs can drive a 37.5 load directly.
V_DAC[4]
193
A
Video DAC output #4. This is a high-impedance current source output. These outputs can drive a 37.5 load directly.
VDD_TVA2 V_DAC[5]
194 195
S A
TV DAC power supply #2 Video DAC output #5. This is a high-impedance current source output. These outputs can drive a 37.5 load directly.
VSS_TVA2 PLL_AVDD LPFO LPFN VREFO PDFLT FDFLT LPFNIN LGIN PLL_DS_AVSS RFI CNIN SLVL DS_AVDD RF_AVDD GMRES AGCCAP
196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212
S S A A A A A A A S A A A S S A A
TV DAC ground pin #2 Servo PLL 3.3V power NC pin NC pin
Servo PLL/Data-slicer ground
Servo Data slicer 3.3V power Servo RF 3.3V power External reference resistor input. External AGC capacitor connected to ground.
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Preliminary
SPHE8281D/Dx
Symbol RFRP RFO FLTIP FLTIN Pin No. 213 214 215 216 I/O O O I I RFRP signal output. RF signal output. Differential RF equalizer input #P Differential RF equalizer input #N Description
Note: Please reference SPHE802D servo datasheet for servo related information.
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Preliminary
SPHE8281D/Dx
5.FUNCTIONAL DESCRIPTIONS
SPHE8281D is a highly integrated system-on-chip DVD player SoC design. It includes DVD/CD front-end RF, read-channel, data decoder, servo controller, host controller, MPEG1/2 video decoder, programmable audio decoder, programmable peripheral controller, audio DAC and multi-format TV-encoder on a single chip. Module-level stop-operation: SPHE8281D provides a function to turn off specific module from operating. Without explicit wake-up, the hardware module will remain static and consume little power. System-level doze: For maximum power-saving, firmware could fine-tune system
5.1. PLL and ClockGen
SPHE8281D contains multiple PLLs to generate system clock and audio reference clocks. All the PLLs reference a single external
performance according to system task.
5.3. Embedded 32-bit RISC Controller
SPHE8281D includes a powerful 32-bit RISC processor as the host controller. This host controller is utilized to manage servo control, decoding tasks as well as UI tasks. It can access to all the memory and devices, cooperate between processor systems. Audio decoder and I/O processor handshake with RISC processor
27MHz clock or crystal to generate the required clocks. System clock is then derived from division of the system PLL output.
CLKI 27MHz
PLLv
Fractional multiples of CLKI
SYSCLK_GEN
/2, /4 ~ /65536
SYSCLK
through the mailbox registers.
Optional video clock in
VIDCLK_GEN
VIDCLK
mailbox (16x16)
Audio decoder
RISC controller
PLLa supports two center frequencies (for both 48kHz family and 44.1kHz family) and generates required audio clocks from the audio system clock.
Figure 5-1 Communication between processors
mailbox (16x8)
I/O processor
The RISC processor is equipped with instruction and data caches.
CLKI 27MHz
PLLa #1 147.456MHz 135.4752MHz
XCK AUDCLK GEN ADCLK IECCLK
These caches can accelerate accesses to the SDRAM or ROM cacheable regions.
I-CACHE
RISC32 core
BIU
Processor Local Bus
PLLa #2
CD_CLK
SMMU
Peripheral Control bus
Other modules ROM FLASH SRAM
ROM/Flash interface
5.2. Power Control
SPHE8281D provides various levels of power-control mechanism in order to achieve minimum power consumption. Automatic power-save: Most hardware modules are automatically power-saved when not operating.
D-CACHE
System bus Interface D-RAM DMA
Memory Interface
Figure 5-2 RISC subsystem
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SPHE8281D/Dx
Table: RISC processor local memory configuration Memory I-Cache D-Cache D-RAM/DMA Specification 8kbyte (2-way set associated) 4kbyte (direct-mapped) 1kbyte scratch buffer Table: Device interrupt controller sources Symbol INT_WDOG INT_VSYNC INT_FLD_ACT INT_FLD_SYNC SDRAM, ROM and other devices are mapped to RISC memory spaces as in the following table: INT_HOST INT_TIMER0 INT_TIMER1 Table: RISC memory mapping Memory Range 8000_0000~87ff_ffff a000_0000~a7ff_ffff 8800_0000~8fff_ffff a800_0000~afff_ffff bffe_8000~bffe_ffff bfff_0000~bfff_03ff Description SDRAM (cached) SDRAM (uncached) ROM/FLASH/SRAM (cached) ROM/FLASH/SRAM (uncached) Peripheral control registers DMA buffer INT_TIMER2A INT_TIMER2B INT_TIMER3A INT_TIMER3B INT_TIMERW INT_UART0 INT_VDP0 INT_DSP INT_EXT0 SPHE8281D includes following dedicated RISC peripherals to assist the system tasks: Device interrupt controller: Device interrupt controller takes care of interrupt sources from on-chip devices and off chip sources. For each interrupt source the firmware is able to configure the interrupt behavior between edge-trigger and level-sensitive mode. Watchdog: Watchdog keeps monitoring RISC behavior and whenever firmware is in a deadlock or ill-behaved, the watchdog would trigger system-wise reset and keep the application functioning continuously. Timers There are 4-channel timers and 2 cascade counters for timed tasks. During A/V decoding, system time counters are utilized to synchronize audio and video playback timing. The SPHE8281D provides flexible connections to external ROM, Flash or SRAM (RFS). It can support up to 4 external RFS devices by using different chip-selects (R_CS_B[3:0]). The firmware can configure RFS memory anchor registers and map these devices into locations of RISC memory space. For each memory space it In FLASH mode the INT_EXT1 INT_EXT2 INT_EXT3 INT_IOP INT_AUD Description Watchdog interrupt (if reset disabled) Interrupt when enter vertical resync Interrupt when enter active region Interrupt when leave active region Host device interrupt Timer 0 interrupt Timer 1 interrupt Timer 2 scale interrupt Timer 2 count interrupt Timer 3 scale interrupt Timer 3 count interrupt Watchdog timer interrupt UART0 interrupt Video decoder interrupt DSP interrupt External interrupt #0 External interrupt #1 External interrupt #2 External interrupt #3 IOP interrupt Audio hardware interrupt
5.4. ROM/Flash/SRAM Controller
can be in flash mode or in ISA mode.
access timing is decided by wait-state setting, while in ISA mode the controller will reference external IO_CHRDY input.
RISC subsystem
peripheral control bus
to RISC interrupt
RISC monitor
monitor interrupt
Processor local bus Address translator
Prefetch buffer External ROM interface
Watchdog
Device interrupt controller
watchdog reset
Address sequencer
Timers
timer interrupt
Wait state generation
Figure 5-4 ROM/FLASH/SRAM controller Figure 5-3 RISC dedicated hardware
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Preliminary
SPHE8281D/Dx
ROM/Flash mode
CSB ADDR[] OEB WEB DATA[] Data (read)
data is sampled at this point oe_setup wait wait
Advanced video decoding and display control mechanism is included to prevent tearing effect.
Address (read)
oe_hold we_setup we_hold
Address (write)
RISC controller
DATA (for write)
Decoding control
Q matrix
input FIFO Output FIFO
Figure 5-5 ROM/FLASH/SRAM mode timing
Variable length decoder
Inverse quantization
ISA MODE
CSB ADDR[] OEB WEB IO_RDY DATA[] Data (read)
data is sampled at this point oe_setup wait iochrdy_hold wait iochrdy_hold
Memory Interface
input buffer output buffer
we_setup we_hold
Address (read)
oe_hold
Address (write)
Motion compensation
Inverse DCT
DATA (for write)
display information
Decoding control
DCT buffer
Figure 5-8 Architecture of video decoding pipeline Figure 5-6 ISA mode timing
5.7. Video Post Processing 5.5. CSS Decryption Hardware
SPHE8281D includes powerful video-post-processing facilities to (Optional) SPHE8281D has built-in CSS decryption hardware DMA support. provide high video quality. It perform following functions: YUV411, YUV420, YUV422 and 8-bit indexed color SIF to CCIR601 interpolation MPEG1 CIF filter MPEG1/2 chroma vertical interpolation to 1/2x horizontal decimation Up to 1/512x vertical decimation Up to 1024x horizontal and vertical expansion Up The video decoder is a hardwired MPEG1/2 decoding datapath. The system architecture is as in the figure. RISC controller is in charge of pre-process and buffering source into SDRAM buffers. Upon correct timing video decoder will start to decode the bitstream and write back reconstructed video frame for playback. Powerful de-interlacing hardware Pan and scan function De-flicker during interlaced display Video contrast/bright/color enhancement During runtime video post-processing hardware will fetch video sources from framebuffer and process the data as in the following figure.
5.6. MPEG Video Decoder
The system incorporates a powerful MPEG video decoding datapath and provides real-time video decoding of MPEGI/II bitstream.
RISC subsystem
de-muxed data
Control bus
Video Decoder
Reconstructed Bitstream in Reference
line buffer Deinterlace input buffer Memory interface de-interlace buffer Vertical filtering and chroma resample CIF and horizontal expansion
data-in
display interface
Memory Interface
Figure 5-7 Interface between RISC and Video decoder
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5.8. Programmable Audio Decoder
The SPHE8281D contains a high-performance 24-bit audio DSP optimized for embedded system applications. This audio DSP processor can fetch operands from two memories and perform multiplication-and-accumulation (MAC) in one cycle. During Data alignment LRCK frame width Data bits Data sign extension Left adjust, I2S, normal format 16b, 24b, 32b, 64b 16b, 18b, 20b, 24b Zero-extended, sign-extended 256fs 384fs SPHE8281D support following audio DAC format combinations: 32k Ok Ok 44.1k Ok Ok 48k Ok Ok 64k Ok Ok 88.2k Ok Ok 96k Ok Ok 192k Ok Ok
execution the DSP fetches instruction from main-memory or IROM, at the same time the ICACHE will store the LRU instructions. Data are loaded from and to main-memory by the cycle-stealing DMA channels.
The DSP works closely with RISC processors by using mailbox registers or shared-memory protocol. When downloaded with different firmware the DSP could support multi-standard audio and act as an accelerator for RISC in some case.
5.10. Audio DAC
SPHE8281D includes a 2-channel 24-bit audio quality DAC for a minimum DVD system.
IROM
Inst. Cache
5.11. I/O Processor
The SPHE8281D includes an 8-bit micro-controller to help host controller handling I/O jobs. IR, VFD and other slow devices can
Audio Core
Data ROM
Data RAM BIU
be interfaced using this I/O processor.
Memory interface
5.12. SDRAM Controller
SDRAM controller in SPHE8281D is designed to meet both flexible and powerful requirements. It can be programmed to use
Data ROM
Data RAM
1Mx16 and 4Mx16 SDRAM chips. For different grade of memory chips it can support flexible timing select to meet different SDRAM
audio interface controller
Audio Hardware
timing requirements while achieving maximum performance.
The
actual speed of SDRAM interface depends on the system configuration.
Figure 5-10 Audio DSP architecture
SPHE8281D supports SDRAM power-down modes to save dynamic operating power.
5.9. Audio Interface
The audio interface is in charge of servicing DSP and maintaining all audio-related tasks. It would buffer the audio PCM samples and format them to audio DAC and SPDIF formats. Up to 8 channel of digital audio are supported in I2S or normal mode.
5.13. Sub-picture Decoder
For DVD and SVCD sub-picture content SPHE8281D includes an advanced multi-format sub-picture decoder. It supports real-time vertical expansion for PAL/NTSC translation or special effect.
Buffer control Memory Interface Audio Work buffer
5.14. On Screen Display
IEC958 digital input interface ADC ctrl IEC-958 input digital audio input ADC analog in
The on screen display (OSD) function of the SPHE8281D provides an overlay bitmap graphics on the final TV display. Applications can use this function to display specific information over the video display plane without operating on the video source.
PCM playback IEC958
The SPHE8281D can display multiple OSD regions on a single
digital audio output IEC-958 output
display frame, where every OSD regions can be in different size, location and color format. The OSD hardware supports 4, 16, 256 indexed color or 16-bit direct color. OSD regions are stored
Figure 5-11 Audio Interface architecture
in main memory before display. During display, OSD decoder would read these header and data and interpret to be a graphic data that overlay with video to be output to the display interface.
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5.15. Display Interface
The display interface of SPHE8281D mixes the video content generated from video-post-processing, sub-picture-decoder and on-screen-display modules. It also performs content cropping, underflow and overflow correction and overall hue / brightness / contrast adjustment.
5.16. Video DAC
SPHE8281D integrates 4-channel 10-bit high-speed current source DACs operating from 27MHz to 108MHz. These DAC outputs can drive a 37.5-Ohm load directly. Half current, quarter current modes are provided for low power operation using external current amplifiers.
Video active?
5.17. GPIO
Sub-picture blend-factor OSD blend-factor
In SPHE8281D almost every pin that related to selectable features can serve as general-purpose input-output (GPIO) control function. When a pin is programmed to this mode, the RISC controller or the I/O processor can take full control over the direction and
Background color MUX Video framebuffer Sub-picture source data OSD bitmap data MIX
output level by simple firmware programming.
TV data output
MIX
5.18. UART
SPHE8281D provide one UART channel for debugging, firmware upgrading and other user applications. This UART can support standard serial port baud-rate and formats. It also supports auto
Figure 5-12 Display pipeline
baud-rate detection and hardware flow control (CTS/RTS pair).
The video enhancement process is show in following figure:
OSD source
OSD sub-picture analog video TV encoder digital output
Video source
Video post processing
Display interface
video source enhancement and bright/ contrast/color control
DAC gain, linearity adjustment
Figure 5-13 Display pipeline
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6.ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDDIO supply relative to VSS Voltage on VDDK supply relative to VSS Storage Temperature Soldering Temp. (Max. Time) Short circuit current Symbol VIN VDDIO VDDK TSTG TSOLDER IOS Value -0.3 to 5.5 -0.3 to 3.45 -0.3 to 1.90 -55 to 150 240 (for 5 Sec. Max.) 50 Unit V V V C C mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2. DC Operating Conditions
Recommended Operating Conditions (Voltage referenced to VSS=0V, TA=-0 to 70C) Parameter Voltage on VDDK supply relative to VSS Voltage on VDDIO supply relative to VSS Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDDK VDDIO VIH VIL VOH VOL IL Min. 1.70 3.15 2.0 -0.3 2.4 -10 Typ. 1.80 3.30 Max. 1.90 3.45 5.5 0.8 0.4 10 Units V V V V V V uA
6.3. Capacitance
(VDDIO=3.3V, TA=24C, f=108MHz, VREF =1.4V+-200mV) Parameter Input pin capacitance Input pin capacitance Bidirectional pin capacitance Symbol CIN COUT CBIDIR Min. Typ. 3.5 3.5 3.5 Max. Units pF pF pF
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6.4. AC Characteristics 6.4.1. SDRAM interface timing diagrams
tCH 0 CLOCK tCL CKE tCC CS tRAS tRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSH RAS tSS CAS tRCD
tRP
tCCD
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa tRRD
RBb
RAc *Note 1 tCDL
DQ CL=2
CAa0
CAa1
CAa2
CAa3
DBb0
DBb1
DBb2
DBb3
CAc0
CAc1
CAc2
tSAC CL=3 tSLZ DH WE CAa0 CAa1 CAa2 CAa3 DBb0 DBb1 DBb2 DBb3 CAc0 CAc1
DQM
Row Active (A-Bank)
Read (A-Bank)
Row Active (B-Bank) Precharge (A-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
: Don't care
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE CS
HIGH
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa tBDL tRDL DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
WE
DQM
Row Active (A-Bank)
Write (A-Bank)
Burat Stop
Write (A-Bank)
Precharge (A-Bank)
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(Recommended condition for DVD playback is listed in typical condition with f=121.5MHz) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new column address delay Column address to column address delay CLK cycle time *2 CLK to valid SDRAM output delay *2 SDRAM output data hold time *2 CLK high pulse width *3 CLK low pulse width *3 CLK to SDRAM output Low-Z CLK to SDRAM output High-Z
Note: 1.Using maximum values may limit system performance. 2.Width of data window can be estimated from (tCC-tSAC+tOH). 3.Width of clock pulse depends on system clock cycle.
Symbol tRRD tRCD tRP tRAS tRC tCDL tCCD tCC tSAC tOH tCH tCL tSLZ tSHZ
Min. 1 1 1 1 1 1 1 6 1 -
Typ. 2 2 2 5 8 1 1 8.2 6.0 2 3 3 1.0 6.0
Max. 4 *1 4 *1 4 *1 8 *1 32 *1 4 *1 1 1000 6.5 (tCC) (tSAC)
Units System clock cycle System clock cycle System clock cycle System clock cycle System clock cycle System clock cycle System clock cycle ns ns ns ns ns ns ns
6.4.2. ROM / flash interface timing diagrams
ROM Compatible Mode
CSB ADDR[] OEB WEB DATA[]
tACCESS
tACCESS
Address (read)
tWES tDS tDH
Address (write)
tWEH
Data (read)
DATA (for write)
Figure 6-1 ROM / flash interface ROM mode access timing
Parameter ROM / SRAM / flash access time Data setup time for read Data hold time for read Address/data setup time before write strobe Address/data setup time after write strobe
Note: Recommended value when f=121.5MHz
Symbol tACCESS tDS tDH tWS tWH
Min. 2 5 0 0 0
Typ. 8 *1 1 1
Max. 31 31 31
Units System clock cycle ns ns System clock cycle System clock cycle
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ISA Compatible Mode
CSB ADDR[] OEB WEB IO_RDY DATA[]
tACCESS
tACCESS
Address (read)
tWES
Address (write)
tWEH tWAIT tOH tIH
tWAIT
tOH
tIH
Data (read)
Figure 6-2 ROM / flash interface ISA mode access timing
Data (write)
Parameter ISA access time *1 IO_RDY wait time Output hold time Input hold time Address/data setup time before write strobe Address/data setup time after write strobe
Symbol tACCESS tWAIT tOH tIH tWS tWH
Min. 2 0 1 0 0 0
Typ. 1 1
Max. 31 1000 31 31
Units System clock cycle ns System clock cycle ns System clock cycle System clock cycle
Note: After this period of time IO_RDY_B must be stable and indicates correct status of target device.
6.4.3. Audio interface timing diagrams
Some audio interface configuration timing diagrams are shown below.
0
1
22
23
0
1
2
22
23
BCK LRCK AUDATA[]
23 MSB 22 left channel 21 2 1 0 23 22 right channel 21 2 1 0 LSB
LSB MSB
Figure 6-3 Normal mode / 24bit data / 24bit frame / MSB first
0
1
8
9
30
31
0
1
30
31
0
BCK LRCK AUDATA[]
left channel 23 MSB 22 21 2 1 0 LSB right channel 2 1 0
Figure 6-4 Right justified (normal) mode / 24bit data / 32bit frame / MSB first
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SPHE8281D/Dx
0 1 2 22 23 24 31 0 1 2 31 0
BCK LRCK AUDATA[]
23 MSB 22 21 left channel 1 0 LSB 23 22 right channel 21
Figure 6-5 Left justified mode / 24bit data / 32bit frame / MSB first
0
1
2
3
23
24
25
31
0
1
2
3
31
0
BCK LRCK AUDATA[]
D 23 MSB 22 left channel 21 2 1 0 LSB D 23 right channel 22
Figure 6-6 I S mode / 24bit data / 32bit frame
2
0
1
2
22
23
0
1
2
22
23
0
1
BCK LRCK AUDATA[]
D 23 MSB left channel 22 21 2 1 D 0 23 right channel 22 21 2 1 0 LSB
LSB MSB
Figure 6-7 I S mode / 24bit data / 24bit frame
2
Parameter BCK rising to LRCK / AUDATA transition
Symbol tS
Min. -
Typ. 0.5
Max. -
Units System clock cycle
6.4.4. Video timing diagrams
Interlaced Modes
SP active period active line period V blanking period (21) SP active period active line period
Video line number
522 523 524 525
SP line number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 0
24 2
25 4
26 6
27 8
28 10
29 12
473 475 477 479
Video line number
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291
SP line number
474 476 478 active line period SP active period V blanking period (21)
1
3
5
7
9
11
active line period SP active period
Figure 6-8 NTSC (480i) timing diagram
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SPHE8281D/Dx
SP active period active line period V blanking period (23.5) SP active period active line period
Video line number
619 620 621 622 623 624 625
SP line number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 0
24 2
25 4
26 6
27 8
567 569 571 573
307 308 309 310 311 312 313 314 315 316
SP line number
Video line number
317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 1 V blanking period (24) 3 5 7 9
474 476 478 active line period SP active period
active line period SP active period
Figure 6-9 PAL (576i) timing diagram
Progressive Modes
SP active period active line period
SP active period active line period
521 522 523 524 525 476 477 478 479
1
2
3
4
5
6
7
8
9
10
11
12
13
14
44
45 0
46 1
47 2
48 3
49 4
50 5
51 6
Figure 6-10 NTSC (480p) timing diagram
SP active period active line period
SP active period active line period
617 618 619 620 621 622 623 624 625 572 573 574 575
1
2
3
4
5
6
7
8
9
43
44
45 0
46 1
47 2
48 3
49 4
50 5
51 6
Figure 6-11 PAL (576p) timing diagram
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SPHE8281D/Dx
7.PACKAGE/PAD LOCATION
7.1. Outline Dimensions
D D1 D2
e
b
E E1 E2
SUNPLUS SPHE8281D
YYWW
c
L1
A2 A A1
Symbol A A1 A2 D D1 E E1 R2 R1 1 2 3 c L L1 S
Unit: Millimeter
Min. 0.05 1.35 26.00 BSC. 24.00 BSC. 26.00 BSC. 24.00 BSC. 0.08 0.08 0O 0O 11
O
Nom. 1.40 26.00 BSC. 24.00 BSC. 26.00 BSC. 24.00 BSC. 3.5 O 12
O
Max. 1.60 0.15 1.45 26.00 BSC. 24.00 BSC. 26.00 BSC. 24.00 BSC. 0.20 7O 13 O 13 O 0.20 0.75 1.00 REF -
11 O 0.09 0.45 1.00 REF 0.20
12 O 0.60 1.00 REF -
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SPHE8281D/Dx
8.DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, expressed, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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Preliminary
SPHE8281D/Dx
9.REVISION HISTORY
Date MAY. 19, 2005
Revision # 0.1 Original
Description
Page 35
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MAY. 19, 2005 Preliminary Version: 0.1

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